Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics. This bookteaches the fundamentals of electrical overstress and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design. It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in specific technologies, circuits, and chips. The book is unique in covering the EOS manufacturing issues from on-chip design and electronic design automation to factory-level EOS program management in today's modern world.Look inside for extensive coverage on:Fundamentals of electrical overstress, from EOS physics, EOS time scales, safe operating area (SOA), to physical models for EOS phenomenaEOS sources in today's semiconductor manufacturing environment, and EOS program management, handling and EOS auditing processing to avoid EOS failuresEOS failures in both semiconductor devices, circuits and systemDiscussion of how to distinguish between EOS events, and electrostatic discharge (ESD) events (e.g. such as human body model (HBM), charged device model (CDM), cable discharge events (CDM), charged board events (CBE), to system level IEC 61000-4-2 test events)EOS protection on-chip design practices and how they differ from ESD protection networks and solutionsDiscussion of EOS system level concerns in printed circuit boards (PCB), and manufacturing equipmentExamples of EOS issues in state-of-the-art digital, analog and power technologies including CMOS, LDMOS, and BCDEOS design rule checking (DRC), LVS, and ERC electronic design automation (EDA) and how it is distinct from ESD EDA systemsEOS testing and qualification techniques, andPractical off-chip ESD protection and system level solutions to provide more robust systemsElectrical Overstress (EOS): Devices, Circuits and Systems is a continuation of the author's series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the nano-electronic era.
A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD designThis book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design. It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect presents the additional challenges associated with the design of adequate and effective ESD protection elements and schemes. A comprehensive list of practical application examples is used to demonstrate the successful combination of both techniques and any potential design trade-offs. Chapter One looks at analog design discipline, including layout and analog matching and analog layout design practices. Chapter Two discusses analog design with circuits, examining: single transistor amplifiers; multi-transistor amplifiers; active loads and more. The third chapter covers analog design layout (also MOSFET layout), before Chapters Four and Five discuss analog design synthesis. The next chapters introduce the reader to analog-digital mixed signal design synthesis, analog signal pin ESD networks, and analog ESD power clamps. Chapter Nine, the last chapter, covers ESD design in analog applications.Clearly describes analog design fundamentals (circuit fundamentals) as well as outlining the various ESD implicationsCovers a large breadth of subjects and technologies, such as CMOS, LDMOS, BCD, SOI, and thick body SOIEstablishes an "ESD analog design" discipline that distinguishes itself from the alternative ESD digital design focusFocuses on circuit and circuit design applicationsAssessible, with the artwork and tutorial style of the ESD book seriesPowerPoint slides are available for university faculty membersEven in the world of digital circuits, analog and power circuits are two very important but under-addressed topics, especially from the ESD aspect. Dr. Voldman's new book will serve as an essential and practical guide to the greater IC community. With high practical and academic values this book is a "bible" for professionals, graduate students, device and circuit designers for investigating the physics of ESD and for product designs and testing.
Electrostatic discharge (ESD) continues to impact semiconductor manufacturing, semiconductor components and systems, as technologies scale from micro- to nano electronics. This book introduces the fundamentals of ESD, electrical overstress (EOS), electromagnetic interference (EMI), electromagnetic compatibility (EMC), and latchup, as well as provides a coherent overview of the semiconductor manufacturing environment and the final system assembly. It provides an illuminating look into the integration of ESD protection networks followed by examples in specific technologies, circuits, and chips.The text is unique in covering semiconductor chip manufacturing issues, ESD semiconductor chip design, and system problems confronted today as well as the future of ESD phenomena and nano-technology.Look inside for extensive coverage on:The fundamentals of electrostatics, triboelectric charging, and how they relate to present day manufacturing environments of micro-electronics to nano-technology Semiconductor manufacturing handling and auditing processing to avoid ESD failures ESD, EOS, EMI, EMC, and latchup semiconductor component and system level testing to demonstrate product resilience from human body model (HBM), transmission line pulse (TLP), charged device model (CDM), human metal model (HMM), cable discharge events (CDE), to system level IEC 61000-4-2 testsESD on-chip design and process manufacturing practices and solutions to improve ESD semiconductor chip solutions, also practical off-chip ESD protection and system level solutions to provide more robust systemsSystem level concerns in servers, laptops, disk drives, cell phones, digital cameras, hand held devices, automobiles, and space applicationsExamples of ESD design for state-of-the-art technologies, including CMOS, BiCMOS, SOI, bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, smart power, magnetic recording technology, micro-machines (MEMs) to nano-structuresESD Basics: From Semiconductor Manufacturing to Product Use complements the author's series of books on ESD protection. For those new to the field, it is an essential reference and a useful insight into the issues that confront modern technology as we enter the Nano-electronic Era.
Electrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics.This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a 'top-down' design approach.Look inside for extensive coverage on:integration of cores, power bussing, and signal pins in DRAM, SRAM, CMOS image processing chips, microprocessors, analog products, RF components and how the integration influences ESD design and integrationarchitecturing of mixed voltage, mixed signal, to RF design for ESD analysisfloorplanning for peripheral and core I/O designs, and the implications on ESD and latchupguard ring integration for both a 'bottom-up' and 'top-down' methodology addressing I/O guard rings, ESD guard rings, I/O to I/O, and I/O to coreclassification of ESD power clamps and ESD signal pin circuitry, and how to make the correct choice for a given semiconductor chipexamples of ESD design for the state-of-the-art technologies discussed, including CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, and smart powerpractical methods for the understanding of ESD circuit power distribution, ground rule development, internal bus distribution, current path analysis, quality metricsESD: Design and Synthesis is a continuation of the author's series of books on ESD protection. It is an essential reference for: ESD, circuit, and semiconductor engineers; design synthesis team leaders; layout design, characterisation, floorplanning, test and reliability engineers; technicians; and groundrule and test site developers in the manufacturing and design of semiconductor chips.It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, and manufacturing sciences, and on courses involving the design of ESD devices, chips and systems. This book offers a useful insight into the issues that confront modern technology as we enter the nano-electronic era.
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